100字范文 > Zynq-Linux移植学习笔记之34-使用PCS/PMA IP核配置网络

Zynq-Linux移植学习笔记之34-使用PCS/PMA IP核配置网络

时间：2020-11-03 12:45:18

1、硬件设计

设计图如下，zynq PS ETH1连接PCS/PMA IP核。

这里PCS/PMA IP核相当于PHY，外部通过PCB连接到光模块。IP核的对应配置如下：

上面重要的部分是PHY的地址1.

2、uboot设计

在uboot中启用双网卡，需要修改zynq-common.h和zynq-zc70x.h两个配置文件

首先在zynq-zc70x.h中增加GEM1并且设置PHY地址为1

然后修改zynq-common.h文件，增加CONFIG_HAS_ETH1并设置eth1addr环境变量地址

在zynq_gem.c中增加针对不同网卡的配置

源码如下

/** (C) Copyright Michal Simek** Michal SIMEK <monstr@monstr.eu>** Based on Xilinx gmac driver:* (C) Copyright Xilinx** SPDX-License-Identifier:GPL-2.0+*/#include <common.h>#include <net.h>#include <config.h>#include <malloc.h>#include <asm/io.h>#include <phy.h>#include <miiphy.h>#include <watchdog.h>#include <asm/arch/hardware.h>#include <asm/arch/sys_proto.h>/* Bit/mask specification */#define ZYNQ_GEM_PHYMNTNC_OP_MASK0x40020000 /* operation mask bits */#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK0x20000000 /* read operation */#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK0x10000000 /* write operation */#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK23 /* Shift bits for PHYAD */#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK18 /* Shift bits for PHREG */#define ZYNQ_GEM_RXBUF_EOF_MASK0x00008000 /* End of frame. */#define ZYNQ_GEM_RXBUF_SOF_MASK0x00004000 /* Start of frame. */#define ZYNQ_GEM_RXBUF_LEN_MASK0x00003FFF /* Mask for length field */#define ZYNQ_GEM_RXBUF_WRAP_MASK0x00000002 /* Wrap bit, last BD */#define ZYNQ_GEM_RXBUF_NEW_MASK0x00000001 /* Used bit.. */#define ZYNQ_GEM_RXBUF_ADD_MASK0xFFFFFFFC /* Mask for address *//* Wrap bit, last descriptor */#define ZYNQ_GEM_TXBUF_WRAP_MASK0x40000000#define ZYNQ_GEM_TXBUF_LAST_MASK0x00008000 /* Last buffer */#define ZYNQ_GEM_NWCTRL_TXEN_MASK0x00000008 /* Enable transmit */#define ZYNQ_GEM_NWCTRL_RXEN_MASK0x00000004 /* Enable receive */#define ZYNQ_GEM_NWCTRL_MDEN_MASK0x00000010 /* Enable MDIO port */#define ZYNQ_GEM_NWCTRL_STARTTX_MASK0x00000200 /* Start tx (tx_go) */#define ZYNQ_GEM_NWCFG_SPEED1000x000000001 /* 100 Mbps operation */#define ZYNQ_GEM_NWCFG_SPEED10000x000000400 /* 1Gbps operation */#define ZYNQ_GEM_NWCFG_FDEN0x000000002 /* Full Duplex mode */#define ZYNQ_GEM_NWCFG_FSREM0x000020000 /* FCS removal */#define ZYNQ_GEM_NWCFG_MDCCLKDIV0x000080000 /* Div pclk by 32, 80MHz */#define ZYNQ_GEM_NWCFG_MDCCLKDIV20x0000c0000 /* Div pclk by 48, 120MHz */#define ZYNQ_GEM_NWCFG_INIT(ZYNQ_GEM_NWCFG_FDEN | \ZYNQ_GEM_NWCFG_FSREM | \ZYNQ_GEM_NWCFG_MDCCLKDIV)#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK0x00000004 /* PHY management idle */#define ZYNQ_GEM_DMACR_BLENGTH0x00000004 /* INCR4 AHB bursts *//* Use full configured addressable space (8 Kb) */#define ZYNQ_GEM_DMACR_RXSIZE0x00000300/* Use full configured addressable space (4 Kb) */#define ZYNQ_GEM_DMACR_TXSIZE0x00000400/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */#define ZYNQ_GEM_DMACR_RXBUF0x00180000#define ZYNQ_GEM_DMACR_INIT(ZYNQ_GEM_DMACR_BLENGTH | \ZYNQ_GEM_DMACR_RXSIZE | \ZYNQ_GEM_DMACR_TXSIZE | \ZYNQ_GEM_DMACR_RXBUF)/* Use MII register 1 (MII status register) to detect PHY */#define PHY_DETECT_REG 1/* Mask used to verify certain PHY features (or register contents)* in the register above:* 0x1000: 10Mbps full duplex support* 0x0800: 10Mbps half duplex support* 0x0008: Auto-negotiation support*/#define PHY_DETECT_MASK 0x1808/* TX BD status masks */#define ZYNQ_GEM_TXBUF_FRMLEN_MASK0x000007ff#define ZYNQ_GEM_TXBUF_EXHAUSTED0x08000000#define ZYNQ_GEM_TXBUF_UNDERRUN0x10000000/* Clock frequencies for different speeds */#define ZYNQ_GEM_FREQUENCY_102500000UL#define ZYNQ_GEM_FREQUENCY_10025000000UL#define ZYNQ_GEM_FREQUENCY_1000125000000UL/* Device registers */struct zynq_gem_regs {u32 nwctrl; /* Network Control reg */u32 nwcfg; /* Network Config reg */u32 nwsr; /* Network Status reg */u32 reserved1;u32 dmacr; /* DMA Control reg */u32 txsr; /* TX Status reg */u32 rxqbase; /* RX Q Base address reg */u32 txqbase; /* TX Q Base address reg */u32 rxsr; /* RX Status reg */u32 reserved2[2];u32 idr; /* Interrupt Disable reg */u32 reserved3;u32 phymntnc; /* Phy Maintaince reg */u32 reserved4[18];u32 hashl; /* Hash Low address reg */u32 hashh; /* Hash High address reg */#define LADDR_LOW0#define LADDR_HIGH1u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */u32 match[4]; /* Type ID1 Match reg */u32 reserved6[18];u32 stat[44]; /* Octects transmitted Low reg - stat start */};/* BD descriptors */struct emac_bd {u32 addr; /* Next descriptor pointer */u32 status;};int net_base_addr;#define RX_BUF 3/* Page table entries are set to 1MB, or multiples of 1MB* (not < 1MB). driver uses less bd's so use 1MB bdspace.*/#define BD_SPACE0x100000/* BD separation space */#define BD_SEPRN_SPACE64/* Initialized, rxbd_current, rx_first_buf must be 0 after init */struct zynq_gem_priv {struct emac_bd *tx_bd;struct emac_bd *rx_bd;char *rxbuffers;u32 rxbd_current;u32 rx_first_buf;int phyaddr;u32 emio;int init;struct phy_device *phydev;struct mii_dev *bus;};static inline int mdio_wait(struct eth_device *dev){struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;u32 timeout = 20000;/* Wait till MDIO interface is ready to accept a new transaction. */while (--timeout) {if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)break;WATCHDOG_RESET();}if (!timeout) {printf("%s: Timeout\n", __func__);return 1;}return 0;}static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,u32 op, u16 *data){u32 mgtcr;struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;if (mdio_wait(dev))return 1;/* Construct mgtcr mask for the operation */mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK)| *data;/* Write mgtcr and wait for completion */writel(mgtcr, &regs->phymntnc);if (mdio_wait(dev))return 1;if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)*data = readl(&regs->phymntnc);return 0;}static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val){return phy_setup_op(dev, phy_addr, regnum,ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);}static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data){return phy_setup_op(dev, phy_addr, regnum,ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);}#ifndef CONFIG_PHYLIBstatic int phy_rst(struct eth_device *dev){struct zynq_gem_priv *priv = dev->priv;u16 tmp;phyread(dev, priv->phyaddr, 0, &tmp);tmp |= 0x8000;phywrite(dev, priv->phyaddr, 0, tmp);phyread(dev, priv->phyaddr, 0, &tmp);while (tmp & 0x8000) {putc('.');if (ctrlc())return 1;phyread(dev, priv->phyaddr, 0, &tmp);}puts("\nPHY reset complete.\n");return 0;}#endifstatic void phy_negotiat(struct eth_device *dev){struct zynq_gem_priv *priv = dev->priv;u16 control;u16 status;u16 temp;u16 timeout_counter=0;phywrite(dev,priv->phyaddr, 22, 2);phyread(dev, priv->phyaddr, 21, &control);control |= 0x0030;phywrite(dev, priv->phyaddr, 21, control);phywrite(dev, priv->phyaddr, 22, 0);phyread(dev, priv->phyaddr, 4, &control);control |= 0x0800;control |= 0x0400;control |= (0x0100 | 0x0080);control |= (0x0040 | 0x0020);phywrite(dev, priv->phyaddr, 4, control);phyread(dev, priv->phyaddr, 9,&control);control |= 0x0300;phywrite(dev, priv->phyaddr, 9,control);phywrite(dev, priv->phyaddr, 22, 0);phyread(dev, priv->phyaddr, 16,&control);control |= (7 << 12);/* max number of gigabit attempts */control |= (1 << 11);/* enable downshift */phywrite(dev, priv->phyaddr, 16,control);phyread(dev, priv->phyaddr, 0, &control);control |= 0x1000;control |= 0x0200;phywrite(dev, priv->phyaddr, 0, control);phyread(dev, priv->phyaddr, 0, &control);control |= 0x8000;phywrite(dev, priv->phyaddr, 0, control);while (1) {phyread(dev, priv->phyaddr, 0, &control);if (control & 0x8000){continue;}else{break;}}phyread(dev, priv->phyaddr, 1, &status);while ( !(status & 0x0020) ) {phyread(dev, priv->phyaddr,19, &temp);//timeout_counter++;//if (timeout_counter == 30) //{//printf("Auto negotiation error\n");//return;//}phyread(dev, priv->phyaddr, 1, &status);}printf("autonegotiation complete.\n");}static void phy_detection(struct eth_device *dev){int i;u16 phyreg;struct zynq_gem_priv *priv = dev->priv;if (priv->phyaddr != -1) {phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);if ((phyreg != 0xFFFF) &&((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {/* Found a valid PHY address */debug("Default phy address %d is valid\n",priv->phyaddr);return;} else {debug("PHY address is not setup correctly %d\n",priv->phyaddr);priv->phyaddr = -1;}}debug("detecting phy address\n");if (priv->phyaddr == -1) {/* detect the PHY address */for (i = 31; i >= 0; i--) {phyread(dev, i, PHY_DETECT_REG, &phyreg);if ((phyreg != 0xFFFF) &&((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {/* Found a valid PHY address */priv->phyaddr = i;debug("Found valid phy address, %d\n", i);return;}}}priv->phyaddr = 0;debug("No PHY detected. Assuming a PHY at address 0\r\n");}static int zynq_gem_setup_mac(struct eth_device *dev){u32 i, macaddrlow, macaddrhigh;struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;/* Set the MAC bits [31:0] in BOT */macaddrlow = dev->enetaddr[0];macaddrlow |= dev->enetaddr[1] << 8;macaddrlow |= dev->enetaddr[2] << 16;macaddrlow |= dev->enetaddr[3] << 24;/* Set MAC bits [47:32] in TOP */macaddrhigh = dev->enetaddr[4];macaddrhigh |= dev->enetaddr[5] << 8;for (i = 0; i < 4; i++) {writel(0, &regs->laddr[i][LADDR_LOW]);writel(0, &regs->laddr[i][LADDR_HIGH]);/* Do not use MATCHx register */writel(0, &regs->match[i]);}writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);return 0;}static int zynq_gem_init(struct eth_device *dev, bd_t * bis){u32 i;u16 tmp;unsigned short PhyReg;unsigned long clk_rate = 0;struct phy_device *phydev;const u32 stat_size = (sizeof(struct zynq_gem_regs) -offsetof(struct zynq_gem_regs, stat)) / 4;struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;struct zynq_gem_priv *priv = dev->priv;const u32 supported = SUPPORTED_10baseT_Half |SUPPORTED_10baseT_Full |SUPPORTED_100baseT_Half |SUPPORTED_100baseT_Full |SUPPORTED_1000baseT_Half |SUPPORTED_1000baseT_Full;if (!priv->init) {/* Disable all interrupts */writel(0xFFFFFFFF, &regs->idr);/* Disable the receiver & transmitter */writel(0, &regs->nwctrl);writel(0, &regs->txsr);writel(0, &regs->rxsr);writel(0, &regs->phymntnc);/* Clear the Hash registers for the mac address* pointed by AddressPtr*/writel(0x0, &regs->hashl);/* Write bits [63:32] in TOP */writel(0x0, &regs->hashh);/* Clear all counters */for (i = 0; i <= stat_size; i++)readl(&regs->stat[i]);/* Setup RxBD space */memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));for (i = 0; i < RX_BUF; i++) {priv->rx_bd[i].status = 0xF0000000;priv->rx_bd[i].addr =((u32)(priv->rxbuffers) +(i * PKTSIZE_ALIGN));}/* WRAP bit to last BD */priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;/* Write RxBDs to IP */writel((u32)priv->rx_bd, &regs->rxqbase);/* Setup for DMA Configuration register */writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);/* Setup for Network Control register, MDIO, Rx and Tx enable */setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);priv->init++;}//debug("phy detection.\n");//phy_detection(dev);//phy_rst(dev);//phy_negotiat(dev);if(net_base_addr==0xe000b000){priv->phyaddr=0;//change to page 0phyread(dev, priv->phyaddr, 22, &PhyReg);PhyReg = PhyReg & 0xfffe;phywrite(dev, priv->phyaddr, 22, PhyReg);phyread(dev, priv->phyaddr, 20, &PhyReg);PhyReg = PhyReg | 0x82;phywrite(dev, priv->phyaddr, 20, PhyReg);/* reset phy */phyread(dev, priv->phyaddr, 0, &PhyReg);PhyReg |= 0x8000;phywrite(dev, priv->phyaddr, 0, PhyReg);for(i=0;i<1000000000;i++); //Delayphyread(dev, priv->phyaddr, 0, &PhyReg);PhyReg |= 0x1000;PhyReg |= 0x0200;PhyReg &= 0xFBFF;phywrite(dev, priv->phyaddr, 0, PhyReg);phyread(dev, priv->phyaddr, 1, &PhyReg);while ( !(PhyReg & 0x0020) ) {phyread(dev, priv->phyaddr, 1, &PhyReg);}printf("GEM0 autonegotiation complete.\n");}else{#if 1priv->phyaddr=1;phyread(dev, priv->phyaddr, 0, &PhyReg);PhyReg |= 0x1000;PhyReg |= 0x0200;PhyReg &= 0xFBFF;phywrite(dev, priv->phyaddr, 0, PhyReg);phyread(dev, priv->phyaddr, 1, &PhyReg);while ( !(PhyReg & 0x0020) ) {phyread(dev, priv->phyaddr, 1, &PhyReg);}printf("GEM1 autonegotiation complete.\n");#endif}puts("GEM link speed is 1000Mbps\n");writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, &regs->nwcfg);setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |ZYNQ_GEM_NWCTRL_TXEN_MASK);return 0;}static int zynq_gem_send(struct eth_device *dev, void *ptr, int len){u32 addr, size;struct zynq_gem_priv *priv = dev->priv;struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;/* setup BD */writel((u32)priv->tx_bd, &regs->txqbase);/* Setup Tx BD */memset(priv->tx_bd, 0, sizeof(struct emac_bd));priv->tx_bd->addr = (u32)ptr;priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |ZYNQ_GEM_TXBUF_LAST_MASK;addr = (u32) ptr;addr &= ~(ARCH_DMA_MINALIGN - 1);size = roundup(len, ARCH_DMA_MINALIGN);flush_dcache_range(addr, addr + size);barrier();/* Start transmit */setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);/* Read TX BD status */if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)printf("TX underrun\n");if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)printf("TX buffers exhausted in mid frame\n");return 0;}/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */static int zynq_gem_recv(struct eth_device *dev){int frame_len;struct zynq_gem_priv *priv = dev->priv;struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];struct emac_bd *first_bd;if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))return 0;if (!(current_bd->status &(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {printf("GEM: SOF or EOF not set for last buffer received!\n");return 0;}frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;if (frame_len) {u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;addr &= ~(ARCH_DMA_MINALIGN - 1);u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);invalidate_dcache_range(addr, addr + size);NetReceive((u8 *)addr, frame_len);if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)priv->rx_first_buf = priv->rxbd_current;else {current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;current_bd->status = 0xF0000000; /* FIXME */}if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {first_bd = &priv->rx_bd[priv->rx_first_buf];first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;first_bd->status = 0xF0000000;}if ((++priv->rxbd_current) >= RX_BUF)priv->rxbd_current = 0;}return frame_len;}static void zynq_gem_halt(struct eth_device *dev){struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);}static int zynq_gem_miiphyread(const char *devname, uchar addr,uchar reg, ushort *val){struct eth_device *dev = eth_get_dev();int ret;ret = phyread(dev, addr, reg, val);debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);return ret;}static int zynq_gem_miiphy_write(const char *devname, uchar addr,uchar reg, ushort val){struct eth_device *dev = eth_get_dev();debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);return phywrite(dev, addr, reg, val);}int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio){struct eth_device *dev;struct zynq_gem_priv *priv;void *bd_space;printf("zynq_gem_initialize: baseAddr = 0x%x, phyAddr = 0x%x.\n",base_addr,phy_addr);net_base_addr=base_addr;dev = calloc(1, sizeof(*dev));if (dev == NULL)return -1;dev->priv = calloc(1, sizeof(struct zynq_gem_priv));if (dev->priv == NULL) {free(dev);return -1;}priv = dev->priv;/* Align rxbuffers to ARCH_DMA_MINALIGN */priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);/* Align bd_space to 1MB */bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);/* Initialize the bd spaces for tx and rx bd's */priv->tx_bd = (struct emac_bd *)bd_space;priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);priv->phyaddr = phy_addr;priv->emio = emio;sprintf(dev->name, "Gem.%x_%x", base_addr,phy_addr);dev->iobase = base_addr;dev->init = zynq_gem_init;dev->halt = zynq_gem_halt;dev->send = zynq_gem_send;dev->recv = zynq_gem_recv;dev->write_hwaddr = zynq_gem_setup_mac;eth_register(dev);#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)debug("zynq_gem MII init.\n");miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);priv->bus = miiphy_get_dev_by_name(dev->name);#endifzynq_gem_init(dev,bis);return 1;}

3、devicetree设置

devicetree中需要设置ETH1节点下的PHY配置信息，如下：

可以通过修改产生devicetree的相应的配置文件得到

完整的devicetree如下

/dts-v1/;/ {#address-cells = <0x1>;#size-cells = <0x1>;compatible = "xlnx,zynq-7000";cpus {#address-cells = <0x1>;#size-cells = <0x0>;cpu@0 {compatible = "arm,cortex-a9";device_type = "cpu";reg = <0x0>;clocks = <0x1 0x3>;clock-latency = <0x3e8>;cpu0-supply = <0x2>;operating-points = <0xa4cb8 0xf4240 0x5265c 0xf4240>;};cpu@1 {compatible = "arm,cortex-a9";device_type = "cpu";reg = <0x1>;clocks = <0x1 0x3>;};};fpga-full {compatible = "fpga-region";fpga-mgr = <0x3>;#address-cells = <0x1>;#size-cells = <0x1>;ranges;};pmu@f8891000 {compatible = "arm,cortex-a9-pmu";interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;interrupt-parent = <0x4>;reg = <0xf8891000 0x1000 0xf8893000 0x1000>;};fixedregulator {compatible = "regulator-fixed";regulator-name = "VCCPINT";regulator-min-microvolt = <0xf4240>;regulator-max-microvolt = <0xf4240>;regulator-boot-on;regulator-always-on;linux,phandle = <0x2>;phandle = <0x2>;};amba {u-boot,dm-pre-reloc;compatible = "simple-bus";#address-cells = <0x1>;#size-cells = <0x1>;interrupt-parent = <0x4>;ranges;adc@f8007100 {compatible = "xlnx,zynq-xadc-1.00.a";reg = <0xf8007100 0x20>;interrupts = <0x0 0x7 0x4>;interrupt-parent = <0x4>;clocks = <0x1 0xc>;};can@e0008000 {compatible = "xlnx,zynq-can-1.0";status = "disabled";clocks = <0x1 0x13 0x1 0x24>;clock-names = "can_clk", "pclk";reg = <0xe0008000 0x1000>;interrupts = <0x0 0x1c 0x4>;interrupt-parent = <0x4>;tx-fifo-depth = <0x40>;rx-fifo-depth = <0x40>;};can@e0009000 {compatible = "xlnx,zynq-can-1.0";status = "disabled";clocks = <0x1 0x14 0x1 0x25>;clock-names = "can_clk", "pclk";reg = <0xe0009000 0x1000>;interrupts = <0x0 0x33 0x4>;interrupt-parent = <0x4>;tx-fifo-depth = <0x40>;rx-fifo-depth = <0x40>;};gpio@e000a000 {compatible = "xlnx,zynq-gpio-1.0";#gpio-cells = <0x2>;clocks = <0x1 0x2a>;gpio-controller;interrupt-controller;#interrupt-cells = <0x2>;interrupt-parent = <0x4>;interrupts = <0x0 0x14 0x4>;reg = <0xe000a000 0x1000>;emio-gpio-width = <0x40>;gpio-mask-high = <0x0>;gpio-mask-low = <0x5600>;};i2c@e0004000 {compatible = "cdns,i2c-r1p10";status = "okay";clocks = <0x1 0x26>;interrupt-parent = <0x4>;interrupts = <0x0 0x19 0x4>;reg = <0xe0004000 0x1000>;#address-cells = <0x1>;#size-cells = <0x0>;clock-frequency = <0x61a80>;};i2c@e0005000 {compatible = "cdns,i2c-r1p10";status = "okay";clocks = <0x1 0x27>;interrupt-parent = <0x4>;interrupts = <0x0 0x30 0x4>;reg = <0xe0005000 0x1000>;#address-cells = <0x1>;#size-cells = <0x0>;clock-frequency = <0x61a80>;};interrupt-controller@f8f01000 {compatible = "arm,cortex-a9-gic";#interrupt-cells = <0x3>;interrupt-controller;reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;num_cpus = <0x2>;num_interrupts = <0x60>;linux,phandle = <0x4>;phandle = <0x4>;};cache-controller@f8f02000 {compatible = "arm,pl310-cache";reg = <0xf8f02000 0x1000>;interrupts = <0x0 0x2 0x4>;arm,data-latency = <0x3 0x2 0x2>;arm,tag-latency = <0x2 0x2 0x2>;cache-unified;cache-level = <0x2>;};memory-controller@f8006000 {compatible = "xlnx,zynq-ddrc-a05";reg = <0xf8006000 0x1000>;};ocmc@f800c000 {compatible = "xlnx,zynq-ocmc-1.0";interrupt-parent = <0x4>;interrupts = <0x0 0x3 0x4>;reg = <0xf800c000 0x1000>;};serial@e0000000 {compatible = "xlnx,xuartps", "cdns,uart-r1p8";status = "okay";clocks = <0x1 0x17 0x1 0x28>;clock-names = "uart_clk", "pclk";reg = <0xe0000000 0x1000>;interrupts = <0x0 0x1b 0x4>;device_type = "serial";port-number = <0x0>;};serial@e0001000 {compatible = "xlnx,xuartps", "cdns,uart-r1p8";status = "okay";clocks = <0x1 0x18 0x1 0x29>;clock-names = "uart_clk", "pclk";reg = <0xe0001000 0x1000>;interrupts = <0x0 0x32 0x4>;device_type = "serial";port-number = <0x1>;};spi@e0006000 {compatible = "xlnx,zynq-spi-r1p6";reg = <0xe0006000 0x1000>;status = "disabled";interrupt-parent = <0x4>;interrupts = <0x0 0x1a 0x4>;clocks = <0x1 0x19 0x1 0x22>;clock-names = "ref_clk", "pclk";#address-cells = <0x1>;#size-cells = <0x0>;};spi@e0007000 {compatible = "xlnx,zynq-spi-r1p6";reg = <0xe0007000 0x1000>;status = "disabled";interrupt-parent = <0x4>;interrupts = <0x0 0x31 0x4>;clocks = <0x1 0x1a 0x1 0x23>;clock-names = "ref_clk", "pclk";#address-cells = <0x1>;#size-cells = <0x0>;};spi@e000d000 {clock-names = "ref_clk", "pclk";clocks = <0x1 0xa 0x1 0x2b>;compatible = "xlnx,zynq-qspi-1.0";status = "okay";interrupt-parent = <0x4>;interrupts = <0x0 0x13 0x4>;reg = <0xe000d000 0x1000>;#address-cells = <0x1>;#size-cells = <0x0>;is-dual = <0x1>;num-cs = <0x1>;};memory-controller@e000e000 {#address-cells = <0x1>;#size-cells = <0x1>;status = "disabled";clock-names = "memclk", "aclk";clocks = <0x1 0xb 0x1 0x2c>;compatible = "arm,pl353-smc-r2p1";interrupt-parent = <0x4>;interrupts = <0x0 0x12 0x4>;ranges;reg = <0xe000e000 0x1000>;flash@e1000000 {status = "disabled";compatible = "arm,pl353-nand-r2p1";reg = <0xe1000000 0x1000000>;#address-cells = <0x1>;#size-cells = <0x1>;};flash@e2000000 {status = "disabled";compatible = "cfi-flash";reg = <0xe2000000 0x2000000>;#address-cells = <0x1>;#size-cells = <0x1>;};};ethernet@e000b000 {compatible = "cdns,zynq-gem", "cdns,gem";reg = <0xe000b000 0x1000>;status = "okay";interrupts = <0x0 0x16 0x4>;clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;clock-names = "pclk", "hclk", "tx_clk";#address-cells = <0x1>;#size-cells = <0x0>;phy-mode = "rgmii-id";xlnx,ptp-enet-clock = <0x6b49d20>;};ethernet@e000c000 {compatible = "cdns,zynq-gem", "cdns,gem";reg = <0xe000c000 0x1000>;status = "okay";interrupts = <0x0 0x2d 0x4>;clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>;clock-names = "pclk", "hclk", "tx_clk";#address-cells = <0x1>;#size-cells = <0x0>;phy-mode = "gmii";xlnx,ptp-enet-clock = <0x6b49d20>;phy-handle = <0x5>;phy@1 {compatible = "Xilinx PCS/PMA PHY";device_type = "ethernet-phy";xlnx,phy-type = <0x5>;reg = <0x1>;linux,phandle = <0x5>;phandle = <0x5>;};};sdhci@e0100000 {compatible = "arasan,sdhci-8.9a";status = "disabled";clock-names = "clk_xin", "clk_ahb";clocks = <0x1 0x15 0x1 0x20>;interrupt-parent = <0x4>;interrupts = <0x0 0x18 0x4>;reg = <0xe0100000 0x1000>;};sdhci@e0101000 {compatible = "arasan,sdhci-8.9a";status = "disabled";clock-names = "clk_xin", "clk_ahb";clocks = <0x1 0x16 0x1 0x21>;interrupt-parent = <0x4>;interrupts = <0x0 0x2f 0x4>;reg = <0xe0101000 0x1000>;};slcr@f8000000 {#address-cells = <0x1>;#size-cells = <0x1>;compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";reg = <0xf8000000 0x1000>;ranges;linux,phandle = <0x6>;phandle = <0x6>;clkc@100 {#clock-cells = <0x1>;compatible = "xlnx,ps7-clkc";fclk-enable = <0x1>;clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";reg = <0x100 0x100>;ps-clk-frequency = <0x2faf080>;linux,phandle = <0x1>;phandle = <0x1>;};rstc@200 {compatible = "xlnx,zynq-reset";reg = <0x200 0x48>;#reset-cells = <0x1>;syscon = <0x6>;};pinctrl@700 {compatible = "xlnx,pinctrl-zynq";reg = <0x700 0x200>;syscon = <0x6>;};};dmac@f8003000 {compatible = "arm,pl330", "arm,primecell";reg = <0xf8003000 0x1000>;interrupt-parent = <0x4>;interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;#dma-cells = <0x1>;#dma-channels = <0x8>;#dma-requests = <0x4>;clocks = <0x1 0x1b>;clock-names = "apb_pclk";};devcfg@f8007000 {compatible = "xlnx,zynq-devcfg-1.0";interrupt-parent = <0x4>;interrupts = <0x0 0x8 0x4>;reg = <0xf8007000 0x100>;clocks = <0x1 0xc 0x1 0xf 0x1 0x10 0x1 0x11 0x1 0x12>;clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";syscon = <0x6>;linux,phandle = <0x3>;phandle = <0x3>;};efuse@f800d000 {compatible = "xlnx,zynq-efuse";reg = <0xf800d000 0x20>;};timer@f8f00200 {compatible = "arm,cortex-a9-global-timer";reg = <0xf8f00200 0x20>;interrupts = <0x1 0xb 0x301>;interrupt-parent = <0x4>;clocks = <0x1 0x4>;};timer@f8001000 {interrupt-parent = <0x4>;interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;compatible = "cdns,ttc";clocks = <0x1 0x6>;reg = <0xf8001000 0x1000>;};timer@f8002000 {interrupt-parent = <0x4>;interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;compatible = "cdns,ttc";clocks = <0x1 0x6>;reg = <0xf8002000 0x1000>;};timer@f8f00600 {interrupt-parent = <0x4>;interrupts = <0x1 0xd 0x301>;compatible = "arm,cortex-a9-twd-timer";reg = <0xf8f00600 0x20>;clocks = <0x1 0x4>;};usb@e0002000 {compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";status = "disabled";clocks = <0x1 0x1c>;interrupt-parent = <0x4>;interrupts = <0x0 0x15 0x4>;reg = <0xe0002000 0x1000>;phy_type = "ulpi";};usb@e0003000 {compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";status = "disabled";clocks = <0x1 0x1d>;interrupt-parent = <0x4>;interrupts = <0x0 0x2c 0x4>;reg = <0xe0003000 0x1000>;phy_type = "ulpi";};watchdog@f8005000 {clocks = <0x1 0x2d>;compatible = "cdns,wdt-r1p2";interrupt-parent = <0x4>;interrupts = <0x0 0x9 0x1>;reg = <0xf8005000 0x1000>;timeout-sec = <0xa>;};};amba_pl {#address-cells = <0x1>;#size-cells = <0x1>;compatible = "simple-bus";ranges;gpio@41200000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41200000 0x10000>;xlnx,all-inputs = <0x0>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x1>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x2>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x3>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41210000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41210000 0x10000>;xlnx,all-inputs = <0x0>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x1>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x0>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0xc>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41220000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41220000 0x10000>;xlnx,all-inputs = <0x0>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x1>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0xaa>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x8>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41230000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41230000 0x10000>;xlnx,all-inputs = <0x1>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x0>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x0>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x6>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41240000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41240000 0x10000>;xlnx,all-inputs = <0x1>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x0>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x0>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x6>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41250000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41250000 0x10000>;xlnx,all-inputs = <0x1>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x0>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x0>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x4>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41260000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41260000 0x10000>;xlnx,all-inputs = <0x1>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x0>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x0>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x2>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41270000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41270000 0x10000>;xlnx,all-inputs = <0x0>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x1>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x0>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x2>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};gpio@41280000 {#gpio-cells = <0x2>;compatible = "xlnx,xps-gpio-1.00.a";gpio-controller;reg = <0x41280000 0x10000>;xlnx,all-inputs = <0x0>;xlnx,all-inputs-2 = <0x0>;xlnx,all-outputs = <0x1>;xlnx,all-outputs-2 = <0x0>;xlnx,dout-default = <0x1>;xlnx,dout-default-2 = <0x0>;xlnx,gpio-width = <0x1>;xlnx,gpio2-width = <0x20>;xlnx,interrupt-present = <0x0>;xlnx,is-dual = <0x0>;xlnx,tri-default = <0xffffffff>;xlnx,tri-default-2 = <0xffffffff>;};axi_pwm@43c10000 {compatible = "xlnx,axi-pwm-1.0";reg = <0x43c10000 0x10000>;xlnx,s00-axi-addr-width = <0x6>;xlnx,s00-axi-data-width = <0x20>;};xadc_wiz@43c00000 {clock-names = "ref_clk";clocks = <0x1 0x0>;compatible = "xlnx,axi-xadc-1.00.a";reg = <0x43c00000 0x10000>;xlnx,alarm-limit-r0 = <0xb5ed>;xlnx,alarm-limit-r1 = <0x57e4>;xlnx,alarm-limit-r10 = <0x5555>;xlnx,alarm-limit-r11 = <0x5111>;xlnx,alarm-limit-r12 = <0x9999>;xlnx,alarm-limit-r13 = <0x91eb>;xlnx,alarm-limit-r14 = <0x6aaa>;xlnx,alarm-limit-r15 = <0x6666>;xlnx,alarm-limit-r2 = <0xa147>;xlnx,alarm-limit-r3 = <0xca33>;xlnx,alarm-limit-r4 = <0xa93a>;xlnx,alarm-limit-r5 = <0x52c6>;xlnx,alarm-limit-r6 = <0x9555>;xlnx,alarm-limit-r7 = <0xae4e>;xlnx,alarm-limit-r8 = <0x5999>;xlnx,alarm-limit-r9 = <0x5111>;xlnx,configuration-r0 = <0x0>;xlnx,configuration-r1 = <0x2100>;xlnx,configuration-r2 = <0x400>;xlnx,dclk-frequency = <0x64>;xlnx,external-mux = "none";xlnx,external-mux-channel = "VP_VN";xlnx,external-muxaddr-enable = <0x0>;xlnx,fifo-depth = <0x7>;xlnx,has-axi = <0x1>;xlnx,has-axi4stream = <0x0>;xlnx,has-busy = <0x1>;xlnx,has-channel = <0x1>;xlnx,has-convst = <0x0>;xlnx,has-convstclk = <0x0>;xlnx,has-dclk = <0x1>;xlnx,has-drp = <0x0>;xlnx,has-eoc = <0x1>;xlnx,has-eos = <0x1>;xlnx,has-external-mux = <0x0>;xlnx,has-jtagbusy = <0x0>;xlnx,has-jtaglocked = <0x0>;xlnx,has-jtagmodified = <0x0>;xlnx,has-ot-alarm = <0x1>;xlnx,has-reset = <0x0>;xlnx,has-temp-bus = <0x0>;xlnx,has-user-temp-alarm = <0x1>;xlnx,has-vbram-alarm = <0x0>;xlnx,has-vccaux-alarm = <0x1>;xlnx,has-vccddro-alarm = <0x1>;xlnx,has-vccint-alarm = <0x1>;xlnx,has-vccpaux-alarm = <0x1>;xlnx,has-vccpint-alarm = <0x1>;xlnx,has-vn = <0x1>;xlnx,has-vp = <0x1>;xlnx,include-intr = <0x1>;xlnx,sampling-rate = "961538.4615384615";xlnx,sequence-r0 = <0x77e0>;xlnx,sequence-r1 = <0x9f77>;xlnx,sequence-r2 = <0x47e0>;xlnx,sequence-r3 = <0x9f77>;xlnx,sequence-r4 = <0x0>;xlnx,sequence-r5 = <0x0>;xlnx,sequence-r6 = <0x0>;xlnx,sequence-r7 = <0x9f77>;xlnx,sim-file-name = "design";xlnx,sim-file-rel-path = "./";xlnx,sim-file-sel = "Default";xlnx,vaux0 = <0x1>;xlnx,vaux1 = <0x1>;xlnx,vaux10 = <0x1>;xlnx,vaux11 = <0x1>;xlnx,vaux12 = <0x1>;xlnx,vaux13 = <0x0>;xlnx,vaux14 = <0x0>;xlnx,vaux15 = <0x1>;xlnx,vaux2 = <0x1>;xlnx,vaux3 = <0x0>;xlnx,vaux4 = <0x1>;xlnx,vaux5 = <0x1>;xlnx,vaux6 = <0x1>;xlnx,vaux7 = <0x0>;xlnx,vaux8 = <0x1>;xlnx,vaux9 = <0x1>;};};chosen {bootargs = "earlycon";stdout-path = "serial0:115200n8";};aliases {ethernet0 = "/amba/ethernet@e000b000";ethernet1 = "/amba/ethernet@e000c000";serial0 = "/amba/serial@e0000000";serial1 = "/amba/serial@e0001000";spi0 = "/amba/spi@e000d000";};memory {device_type = "memory";reg = <0x0 0x40000000>;};};